Samsung used its FMS 2026 keynote to show a roadmap rather than a product line. The headline items are zHBM, a concept for stacking high bandwidth memory directly on top of an AI accelerator instead of beside it, zNAND-O for edge inference, and V10 BV-NAND, the company’s first NAND architecture built on wafer bonding, with more than 400 layers and roughly 58% higher density than the V9 generation it replaces.
Read the three announcements together and one process technology sits underneath all of them. Samsung is not scaling by adding layers or shrinking cells. It is scaling by bonding wafers together.
What zHBM actually proposes
Today’s HBM sits next to the processor on a silicon interposer. Data travels laterally from the memory stack to the accelerator across a few millimetres of interconnect. zHBM moves the stack on top of the accelerator die, which shortens that path to the vertical distance between two bonded wafers.
Samsung’s claims for the resulting interface are large. Roughly eight times the performance of HBM5, more than ten times the memory density of HBM5, three times the energy efficiency, and a reduction in thermal resistance of more than half. It also proposes that customer-specific IP can be integrated into the interlayer sitting between the memory and the accelerator, which is the interesting part of the pitch and the part that is not about memory at all.
The performance numbers deserve a caveat. HBM5 is not a shipping product with a published specification, so these figures compare one concept against another concept. Samsung began mass production of HBM4 in February on 1c DRAM with a 4nm base die and shipped HBM4E samples in May, which is the real state of the art. zHBM is measured against something two generations past that.
Thermal resistance is the tell
Of the four claims, the one about thermal resistance is the one that explains why zHBM exists as a concept model rather than a product. Memory has stayed beside the processor rather than on top of it largely because of heat. A modern AI accelerator dissipates a kilowatt or more, and DRAM retention degrades sharply with temperature. Putting a DRAM stack directly above the hottest die in the system means the memory has to survive that heat flux while the heat itself has to escape through the memory to reach the heatsink.
Samsung listing a halving of thermal resistance among its headline claims is an acknowledgement that this is the blocker. Whether the number holds under a sustained training workload rather than in simulation is the question that determines if zHBM ever ships. Nobody outside Samsung can answer it yet, and Samsung has not said when they will try.
The NAND side is the part that is real
V10 BV-NAND is the concrete announcement in the release and it will matter sooner. Samsung applied wafer bonding to stack the memory cells, crossing 400 layers and lifting density about 58% over V9, with improvements to read, write and I/O performance. It arrives thirteen years after Samsung introduced V-NAND at the 2013 Flash Memory Summit, which is a useful reminder of how long the vertical NAND architecture has run before needing a structural change.
Kioxia is doing the same thing from a different starting point, showing generation 10 BiCS FLASH at 332 layers using CMOS directly bonded to array. SanDisk and SK hynix rely on through-silicon vias and hybrid bonding for the High Bandwidth Flash specification they published at the same show. Three companies, three product categories, one process dependency.
That convergence is worth more attention than any individual product claim. Bit density gains from stacking alone are getting expensive, and bonding separates the periphery logic from the array so each can be optimised independently. It also moves a growing share of memory value into advanced packaging, which is a different supply chain from the one that has historically constrained memory output.
zNAND-O rounds out the announcement, in four-layer and eight-layer versions aimed at edge AI, where low latency and I/O performance matter more than capacity. It occupies roughly the same conceptual territory as Kioxia’s XL-FLASH, which suggests the low-latency NAND category is about to become competitive rather than remaining a niche one supplier defends.
zHBM is a foundry pitch
The final section of Samsung’s release explains the rest of it. Samsung describes itself as the only integrated device manufacturer with memory, foundry and advanced packaging under one roof, offering one-stop turnkey solutions from design through mass production.
Consider what building a zHBM system would require. You need someone to fabricate the accelerator die, someone to fabricate the DRAM, someone to design the custom interlayer holding the customer’s IP, and someone to bond all of it together with enough yield to be economic. Exactly one company can quote all four line items. zHBM is only buildable as a vertically integrated product, and it is being proposed by the only vertically integrated supplier.
That makes this less a memory announcement than an argument for Samsung Foundry, delivered by Samsung’s memory business at a memory conference. The company’s foundry unit has struggled to win leading-edge logic customers against TSMC on process merit. Offering a memory architecture that only works if you also buy the logic wafer and the packaging is a different route to the same customer, and Samsung’s recent memorandum of understanding with AMD on next-generation AI memory and computing is the shape of what that customer relationship would look like.
Whether anyone signs up is a separate question. The counterargument is that accelerator vendors have spent a decade building supply chains specifically to avoid single-source dependency, and zHBM asks them to accept it across memory, logic and packaging simultaneously. That is a large commitment to make for a concept model with no stated production date.
The number to watch is not the eight-times claim. It is when Samsung puts a date on zHBM samples. Until then the shipping story here is V10 BV-NAND and the 58% density gain, which will show up in bit supply and pricing long before anything is stacked on top of a GPU.