Kioxia America announced that its GP Series PCIe NVMe SSD took the Best of Show award in the Specialized Storage category at FMS: the Future of Memory and Storage, running this week in Santa Clara. Trade show awards are not usually worth a paragraph. This one is, because of what else happened at the same event.
One day before the award, SanDisk and SK hynix published the first technical specification for High Bandwidth Flash through the Open Compute Project. Both announcements are attempts to solve the same problem: GPUs have run out of affordable memory capacity, and HBM is not getting cheaper fast enough. The two approaches have almost nothing else in common.
What the GP1 actually is
The GP1 is built on Kioxia’s XL-FLASH generation 2 low-latency flash, with a PCIe 6.0 interface and NVMe 2.2. Kioxia claims up to 10 million random read IOPS at 512-byte access granularity, with read latency under five microseconds, and a stated roadmap toward 100 million IOPS in later generations. Evaluation samples go to selected customers by the end of 2026.
The number that carries the design is not the 10 million. It is the 512 bytes. Ten million reads per second at 512-byte granularity works out to roughly five gigabytes per second of actual data movement, which is a small fraction of what a PCIe 6.0 link can carry. Kioxia has not built a bandwidth product. It has built a product optimized for the rate at which small, scattered reads can be serviced, and then deliberately left most of the link’s throughput unused.
That profile has a history. Intel’s Optane occupied roughly this position in the hierarchy before it was discontinued in 2022, and its disappearance left a hole that storage vendors have been probing at ever since. VAST Data qualified Kioxia’s earlier FL6 drives for metadata work when Optane supply became a risk. The GP1 is the same idea with an order of magnitude more headroom, and on paper it exceeds Optane comfortably on both access rate and latency.
Two different bets on where flash sits
High Bandwidth Flash takes the opposite route. The published specification defines 8-high and 16-high TSV-stacked NAND assemblies reaching 512GB per device, connected over UCIe, with three performance grades spanning roughly 0.4 to 3.0 terabytes per second. The top grade lands in the same range as an HBM4 stack. Google and Tenstorrent joined the consortium during standardization, which tells you the target is accelerator silicon that does not exist yet.
HBF answers a streaming question. If model weights will not fit in HBM, put them in something with comparable bandwidth and eight to sixteen times the capacity, sitting on the package. That is a sequential read problem, and it is why every HBF discussion is framed around inference rather than training. Weights are static during inference. Flash writes are slow and finite, so a tier that is read almost exclusively is the only version of this that works.
The GP1 answers a scatter question. Key-value cache offload, embedding table lookups, vector index traversal, retrieval against a corpus that does not fit anywhere near the accelerator: these are millions of small independent reads, and they are not limited by bandwidth. They are limited by how many separate accesses the storage tier can complete per second and how long each one takes. A drive delivering five gigabytes per second in 512-byte pieces is more useful for that workload than one delivering fifty gigabytes per second in megabyte-sized ones.
Both are called memory extension. They extend memory for different reasons.
Kioxia is hedging across all three tiers
The GP1 was not Kioxia’s only announcement at the show. It is also exhibiting the XL1, a CXL-attached memory expansion module using XL-FLASH, with evaluation samples going to ecosystem partners in August 2026. And Kioxia has its own high-bandwidth flash effort, stacking up to 32 dies with through-silicon vias for connection to the GPU bus, with Nvidia driving the partner discussions.
That is three positions in the memory hierarchy at once: on the accelerator package, on the memory bus via CXL, and at the end of a PCIe link. Kioxia has not committed to a winner, which is a reasonable posture when nobody knows which tier the software will actually target.
There is an oddity in the competitive picture worth noting. Kioxia and SanDisk jointly own the Japanese fabs that produce both companies’ NAND. They are now backing different architectures for the same emerging tier, out of shared wafer capacity, while SanDisk’s partner on the specification is SK hynix.
The part that has to be true
Optane was not killed by physics. It was killed by the fact that almost nobody rewrote their software to use a tier that might not survive the next product cycle, which left volumes too low to justify the manufacturing. Both of this week’s announcements face that problem again. GPU-direct access to flash requires the inference serving stack to be built around it, and HBF requires accelerator vendors to spend package area on it.
SanDisk and SK hynix have moved first on the ecosystem question by publishing an open specification and pulling in a hyperscaler and a chip designer as consortium members. Kioxia’s answer is that its product runs over an interface every server already has, on drives that plug into slots that already exist, with samples this year. Neither of those is a technical argument. They are both arguments about adoption risk, which is the only argument that matters here.
The award is for a sample drive that ships to a handful of customers by December. Watch instead for the first inference framework that treats a PCIe device as an addressable memory tier rather than as storage. That is the announcement that decides whether any of this becomes a product category.