Marvell Technology is pushing its optical connectivity roadmap further into the 2nm era, announcing what it describes as industry-first demonstrations of several 2nm optical interconnect technologies at ECOC 2026 in Málaga. The developments are significant because AI data centers are rapidly moving toward 3.2T networking and increasingly dense accelerator clusters, making bandwidth, power consumption and the physical limits of copper interconnects major constraints on further scaling.
The headline demonstration is Marvell’s 2nm 400G-per-lane optical PAM4 technology. By doubling lane speed from the 200G-per-lane technology used in current 1.6T architectures, the approach is designed to support the transition toward 3.2T connectivity while reducing power consumption per bit. This is particularly relevant as hyperscalers build larger AI clusters in which thousands of XPUs, CPUs, accelerators and memory resources need to exchange enormous amounts of data.
Marvell is also demonstrating a 2nm 800G ZR/ZR+ optical solution incorporating MACsec security. The system uses Marvell’s Libra 2nm coherent DSP and combines long-distance coherent optical transmission with hardware-based media access control security. That matters as AI infrastructure increasingly spans multiple racks and facilities, where optical links have to deliver not only bandwidth and reach but also security.
Another important demonstration is 1.6T ZR and coherent-lite O-band connectivity using Marvell’s next-generation 2nm DSPs. These technologies are aimed at high-bandwidth connections both within data centers and between facilities. While 1.6T remains below the eventual 3.2T target, the underlying 2nm technology is being positioned as a foundation for the next generation of optical infrastructure.
The most strategically interesting part may be Marvell’s co-packaged optics, or CPO, platform. Marvell is demonstrating a system operating at 102.4 Tbps using 200G-per-lane silicon photonics, with optics integrated directly alongside AI accelerator and switch silicon. As AI clusters become larger and faster, electrical connections increasingly face distance and power limitations. Moving optical conversion closer to the switching or compute silicon can potentially reduce those losses and increase bandwidth density.
The progression of Marvell’s roadmap is worth watching. The company previously introduced 5nm 200G-per-lane Nova DSPs for 1.6T connectivity, followed with its 3nm 1.6T Ara platform, and then moved its Libra coherent DSP to 2nm. The latest demonstrations show Marvell extending that 2nm technology across PAM4, coherent-lite, ZR/ZR+ and CPO architectures rather than relying on a single optical technology.
For MRVL shareholders, the key issue is that this is primarily a technology and product-roadmap announcement rather than an immediate revenue catalyst. The demonstrations do, however, reinforce Marvell’s positioning in one of the most important infrastructure bottlenecks created by AI scaling: moving data efficiently between increasingly powerful compute and networking components. The transition from 1.6T toward 3.2T and eventually higher-speed architectures creates a substantial need for faster optical DSPs, silicon photonics and co-packaged optics.
The bigger opportunity is that AI infrastructure is not simply requiring more compute. Every generation of faster accelerators creates corresponding demands on the network connecting those accelerators. Marvell’s 2nm optical roadmap is aimed directly at that problem, with lower power per bit and greater bandwidth density becoming increasingly important as hyperscalers scale AI clusters. The ECOC demonstrations therefore provide another indication that Marvell is positioning its connectivity business around the next wave of AI infrastructure spending rather than just the current 1.6T generation.