SK hynix and Sandisk published the first standard specifications for High Bandwidth Flash on August 3, timed to the opening of FMS 2026 at the Santa Clara Convention Center. The spec covers capacities up to 512GB across 8-high and 16-high NAND die stacks, three bandwidth grades running from roughly 0.4TB/s to 3.0TB/s, and a set of packaging, reliability and software I/O guidelines for the die stack process. It went out through the Open Compute Project rather than as a proprietary SK hynix document. Google and Tenstorrent are in the consortium, which launched only six months ago in February, following the original two-company standardization partnership struck in August 2025.
The single most consequential line in the release is the interconnect choice. HBF attaches over UCIe, the open chiplet interface, which means the technology is not tied to one accelerator vendor or one packaging house. GPUs, CPUs and custom ASICs can all designate an HBF stack as an attached tier. Tenstorrent sitting in the consortium alongside Google is the signal worth reading: the demand side of the AI silicon market wants this to exist, and wants it to exist as a commodity interface rather than a negotiated bilateral supply arrangement.
What the spec actually does to the memory hierarchy
HBF occupies the gap between HBM and the SSD. It borrows HBM’s stacking and near-processor placement, and it borrows NAND’s cost per bit and areal density. The result is a capacity tier that can be addressed at bandwidths approaching the low end of the HBM range while carrying an order of magnitude more capacity per package.
That gap is where inference workloads are currently bleeding money. Model weights, KV caches, retrieval indices and long-context state all want residency close to the compute and none of them fit in HBM at any sane cost. Today they spill to SSD across PCIe, and the latency penalty is why serving costs scale badly with context length. Kim Chun-sung, who heads Solution Development at SK hynix, framed the pitch as redesigning the overall data processing structure. That is the accurate framing. The keynote on August 4 by Kim and Vice President Kang Uk-song is titled around Tiered Memory in the era of agentic AI, and the August 6 panel puts Sandisk’s Rajeev Nagabhirava and Google DeepMind’s Xiaoyu Ma on stage under the heading of breaking the memory wall. Google DeepMind does not send a senior staff engineer to a storage conference panel about a technology it considers speculative.
Alongside the spec, SK hynix is showing its tenth-generation 375-layer 4D NAND wafer publicly for the first time, claiming 2.5 times the performance per watt of the prior generation, with eSSD mass production slated for early next year.
This is a wafer demand story before it is a product story
The reason this matters for equity holders has nothing to do with HBF revenue in 2027, which will be negligible. It has to do with what the standard does to the shape of NAND bit demand.
HBM did this to DRAM. Stacking consumes wafer area disproportionately, yields worse than monolithic die, and pulls capacity out of the commodity pool, which is why the DRAM shortage became structural rather than cyclical. HBF applies the identical mechanic to NAND. Every gigabyte of HBF capacity is NAND wafer output that never enters the SSD or client market, produced on a process that stacks and packages with the same yield drag. And unlike SSD demand, HBF demand scales with accelerator shipments rather than with data volume, which is a much steeper curve.
The supply side cannot answer quickly. NAND capex was cut hard through the 2023 and 2024 trough, greenfield fab decisions made now produce bits in 2029, and the 375-layer node that makes HBF economically sensible is not in volume production until next year. Kioxia customers were already booking supply two years out earlier this year, which is not behavior you see in a market that expects relief.
The valuation argument
Micron is up more than 200% year to date and Sandisk more than 500%, and the reflexive read on numbers like that is that the trade is late. The multiples say otherwise. Both names trade in the mid-single digits on forward earnings against fiscal 2027 consensus, which is not a peak-cycle multiple. It is the multiple the market assigns when it believes earnings are about to mean-revert.
That is the entire disagreement, and it is a disagreement about the demand curve rather than about the earnings. Memory has been priced as a commodity cyclical for forty years for good reason. The bear case does not require anything to break. It only requires the cycle to behave the way every prior cycle behaved. Mid-single-digit multiples on record earnings are the market pricing that reversion as near certain.
An open HBF standard published through OCP is direct evidence against it. Proprietary technologies wait for one anchor customer and then negotiate. Open standards get designed into multiple silicon roadmaps simultaneously, which is what turns a demand pocket into a demand layer. When NAND stops being the tier below memory and becomes a tier inside it, the addressable market is not the storage attach rate. It is a fraction of accelerator bill of materials, and that fraction gets set by architects who are currently constrained by exactly the bottleneck HBF exists to remove.
The near-term test arrives fast. Sandisk reports on August 5, one day into the show, which puts NAND pricing commentary and any HBF roadmap language directly against this announcement. SK hynix now trades in the US as well, having listed ADRs on NASDAQ, so the entire memory complex is available in one tape for the first time.
What would invalidate this
HBF is a specification with no shipping product, no committed volume and no disclosed pricing. Grade 1 at roughly 0.4TB/s sits far below where HBM4 operates, so the tier only earns its place if the software stack can tolerate the latency and route around NAND’s write endurance limits. That is a serious engineering problem and the software I/O guidelines in the spec are an acknowledgment of it, not a solution to it. Layer count also cuts both ways: 375 layers going to 500 is a deflationary force on cost per bit that can absorb a lot of incremental demand without tightening anything.
And the standard could simply be early. Consortium membership is cheap. Tape-outs are not.