Synopsys and TSMC have widened their partnership with certified design flows for TSMC’s A14 process, new agentic AI features in Synopsys’ tools, and a long list of silicon-proven IP for AI chips. It comes the same week Cadence announced its own TSMC milestones. Both big EDA vendors are racing to be ready for the next nodes.
“Customers require proven IP, intelligent design solutions, and advanced packaging methodologies that work together seamlessly,” says Michael Buehler-Garcia, senior vice president at Synopsys.
Agents inside the design tools
Synopsys is putting agentic AI into its core compilers. Custom Compiler uses it to speed up analog migration, the slow and manual job of moving analog circuits to a new node. Fusion Compiler gets LLM-assisted analysis to help digital designers. 3DIC Compiler uses AI agents to co-optimize chiplet floorplans in multi-die designs.
Chip design teams can’t grow as fast as chip complexity, so the question is how much of the routine work these agents can take off engineers’ hands.
A14 certified, IP on N2P
TSMC has certified Synopsys’ digital and analog flows for A14, including device routing for analog place-and-route. On the IP side, Synopsys lists a string of milestones:
- PCIe 7.0 taped out on N2P
- HBM4 and LPDDR6/5X/5 memory interfaces
- 224G Ethernet PHY
- UCIe die-to-die IP, with 64G completed on 2nm and 3nm, and 32G/40G validated in silicon on an N3P test chip
- One-time programmable memory and on-chip PVT monitoring
Synopsys also supports TSMC’s CoWoS and 3DFabric packaging and TSMC-COUPE for co-packaged optics. That includes flows where photonic and electronic chips are designed together.
Aveek Sarkar of TSMC says the goal is combining certified EDA and proven IP “with our latest process and packaging innovations.” Custom AI accelerators are getting bigger, more modular and more optical, and Synopsys and Cadence both want to be the toolchain those chips get built with.