The week of electronica and SEMICON Europa in Munich brings a wave of chip-tooling announcements. Three from November 9 are worth a look, because each targets a different bottleneck: the engineer writing firmware, the designer putting AI into a chip, and the factory trying to build quantum processors at scale.
Texas Instruments: agents inside the IDE
TI has added agentic AI to its CCStudio development tools, both the standalone IDE and the Visual Studio Code version. The IDE now exposes its functions to AI agents, which can write code, configure peripherals, build, flash the chip and debug, on their own.
The technical point that matters is how TI feeds the model. Instead of hoping a general model knows TI’s parts, it uses Model Context Protocol (MCP) servers to inject the relevant SDK, pin configuration and peripheral data into each request. TI says that cuts hallucinations and sends less context, which lowers latency and token costs. It covers TI’s general-purpose and real-time microcontrollers, wireless connectivity chips and radar systems-on-chip.
The most useful feature is probably the device migration skill. Moving a project from one chip to another means remapping peripherals, changing API calls and fixing the build errors that follow. TI says specialized sub-agents now do that and cut the work from months to days, sometimes hours. TI doesn’t name the AI models it supports, only “industry-standard” agents and models. The tools are available now and CCStudio is a free download. TI is showing them at electronica, November 10 to 13.
The cynical but fair read: migration help also makes it easier to move onto TI parts from a competitor’s. Tooling has always been a way to win designs, and AI agents make that more true.
Expedera and Cadence: two AI blocks working together
Expedera, which licenses neural processing unit designs, is demonstrating its Origin Evolution NPU working alongside Cadence’s Tensilica NeuroEdge 130 AI co-processor. The NPU handles the heavy neural network math. The Cadence block handles the pre- and post-processing and any operations the NPU doesn’t support. Splitting the work that way is meant to save power and cut latency in edge AI chips for phones, cars and edge servers.
This is a pre-silicon simulation, not a chip. There are no benchmarks, no customers and no availability date. Expedera says its NPU designs are already in more than 10 million consumer devices. For chip designers, the value is a pre-validated pairing of two IP blocks that would otherwise take integration work. The two companies will be at ICCAD-Expo in Beijing on November 19 and 20.
EV Group: manufacturing tools for quantum chips
EV Group, the Austrian wafer-bonding and lithography equipment maker, laid out how its tools apply to every main type of qubit. Oxide-free bonding can form superconducting connections between stacked chips. Fusion and oxide-free bonding can put exotic optical materials onto photonic waveguides. Hybrid bonding gives the dense wiring spin qubits need. For trapped-ion systems, EVG co-developed a low-temperature metal bonding process to join ion-trap and photonic chiplets.
EVG is a strategic partner in CHAMP-ION, a Silicon Austria Labs pilot line it calls Europe’s first open-access line for building ion-trap chips at industrial scale, and recently announced a collaboration with Xanadu, the photonic quantum company. There are no orders or revenue figures. The pitch is simple: nobody knows which qubit type will win, so EVG wants to sell to all of them. It is at SEMICON Europa in Munich, November 10 to 13.
The common thread
None of these is a breakthrough on its own. All three are about making hard engineering work faster and more repeatable: firmware with agents, AI chip design with pre-integrated IP, quantum chips with production-grade bonding. That’s usually where real progress shows up before it reaches a product.