"As it prepares to celebrate the 10th year since its inception, RISC-V is showing the most dangerous trait in any competitor, the ability to redefine the ecosystem." Source: How risky is RISC-V to Arm, Intel and the others? Very RISC-V and Open POWER Instruction Set Architecture (ISA) Fortunes are Rising, Market Analysis … [Read more...] about Rise of RISC-V
RISC-V
OneSpin Addresses the Challenges of RISC-V Verification Through Series of Speaking Engagements, Workshop, and Tutorials designed to help developers and integrators effectively verify RISC-V integrity: functional correctness, safety, security, and trust
OneSpin® Solutions, provider of certified IC integrity verification solutions for building functionally correct, safe, secure, and trusted integrated circuits, today announced several technical speaking public engagements focused on the verification of RISC-V processor cores. The series of presentations, workshops, and tutorials will educate developers and integrators of RISC-V … [Read more...] about OneSpin Addresses the Challenges of RISC-V Verification Through Series of Speaking Engagements, Workshop, and Tutorials designed to help developers and integrators effectively verify RISC-V integrity: functional correctness, safety, security, and trust
IAR Systems Updates RISC-V Development Tools With Custom Extensions Support and Code Speed Optimizations
IAR Systems®, the future-proof supplier of software tools and services for embedded development, announces that a new version of the toolchain IAR Embedded Workbench® for RISC-V is now available. Version 1.11 adds support for custom extensions as well as further enhanced optimizations for code execution speed. One of the major benefits of using RISC-V is the flexibility the … [Read more...] about IAR Systems Updates RISC-V Development Tools With Custom Extensions Support and Code Speed Optimizations
OpenPOWER to become Linux Foundation project to advance development of data-driven architectures required for hybrid cloud environments and increasingly intensive workloads
The Linux Foundation, the nonprofit organization enabling mass innovation through open source, today announced that the OpenPOWER Foundation will become a project hosted at The Linux Foundation. The project includes IBM's open POWER Instruction Set Architecture (ISA) and contributed Source Design Implementations required to support data-driven hardware for intensive workloads … [Read more...] about OpenPOWER to become Linux Foundation project to advance development of data-driven architectures required for hybrid cloud environments and increasingly intensive workloads
The Linux Foundation Open Source Summit: IBM will contribute implementation rights to key technologies to the open community
IBM (NYSE: IBM) announced today at The Linux Foundation Open Source Summit that it will be contributing implementation rights to key technologies to the open community, further building upon IBM's long legacy of open source development. IBM is opening the POWER Instruction Set Architecture (ISA), which is critical to how hardware and software work together on POWER. With the … [Read more...] about The Linux Foundation Open Source Summit: IBM will contribute implementation rights to key technologies to the open community
RISC-V gains new performance leader with Alibaba’s 16-core XT 910
http://linuxgizmos.com/risc-v-gains-new-performance-leader-with-alibabas-16-core-xt-910/ RISC-V and Open POWER Instruction Set Architecture (ISA) Fortunes are Rising, Market Analysis … [Read more...] about RISC-V gains new performance leader with Alibaba’s 16-core XT 910
A Whole New World: Apple, Qualcomm, ARM and RISC-V
https://seekingalpha.com/article/4277548-apple-qualcomm-arm-dancing-new-dance, Source: Seeking Alpha Also: How Apple's $1 billion Intel modem purchase happened Top Arm CPU designer moves to Apple Can Arm Survive RISC-V Challenge? RISC-V and Open POWER Instruction Set Architecture (ISA) Fortunes are Rising, Market Analysis … [Read more...] about A Whole New World: Apple, Qualcomm, ARM and RISC-V
RISC-V SoftCPU Contest Winners Demonstrate Cutting-Edge RISC-V Implementations for FPGAs
Contest sponsored by Google, Antmicro, Lattice Semiconductor and Microchip honors four winners for creating ultra-small and high-performance FPGA soft CPU implementations with the RISC-V ISA Today at the RISC-V Summit, the RISC-V Foundation, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set … [Read more...] about RISC-V SoftCPU Contest Winners Demonstrate Cutting-Edge RISC-V Implementations for FPGAs